1. Field of the Invention
The present invention relates to an active matrix display device and, more specifically, to an active matrix display device incorporating driver circuits.
2. Description of the Related Art
The active matrix display device means a display device in which as shown in FIG. 20 pixels are arranged at intersections of a matrix and each pixel is provided with a switching element, and pixel information is controlled by on/off switching of the switching element. The active matrix display device uses a liquid crystal 1 as a display medium. In the invention, a thin-film transistor 2, which is a three-terminal device having the gate, source, and drain, is used as the switching element.
In the matrix, the term xe2x80x9crowxe2x80x9d means a structure in which a scanning line (gate line) 3 extending parallel with the associated row is connected to the gate electrodes of thin-film transistors 2 of the associated row. The term xe2x80x9ccolumnxe2x80x9d means a structure in which a signal line (source line) 4 extending parallel with the associated column is connected to the sources (or drains) of thin-film transistors 2 of the associated column. The circuit for driving the scanning lines 3 is called a scanning line driver circuit, and the circuit for driving the signal lines 4 is called a signal line driver circuit. The thin-film transistor is abbreviated as xe2x80x9cTFTxe2x80x9d.
FIGS. 21A and 21B show a first example of a conventional active matrix liquid crystal display device. Reference numerals 11 denotes an amorphous TFT active matrix, and numerals 12 and 13 denote single crystal silicon driver circuit ICs.
In this active matrix liquid crystal display device, the TFTs are formed by using amorphous silicon, the scanning line and signal line driver circuits are single crystal silicon integrated circuits and are mounted around a glass substrate by means of tabs (see FIG. 21A) or by using a COG (chip on glass) technique (see FIG. 21B).
This type of liquid crystal display device has the following problems.
First, there is a reliability problem because the signal lines and the scanning lines are connected to the active matrix via tabs or bonding wires. For example, in the case of a VGA (video graphic display) display device, the number of signal lines is 1,920 and the number of scanning lines is 480. These numbers are increasing year by year with the increase in resolution.
Second, in the case of producing a view finder for a video camera or a liquid crystal projector, a compact display device is needed. However, for these purposes, a liquid crystal display device using tabs is disadvantageous in terms of a space occupied by it.
To solve the above problems, an active matrix liquid crystal display device using polysilicon TFTs has been developed. FIG. 22 shows its example. In this display device, by using polysilicon TFTs, a signal line driver circuit 17 and a scanning line driver circuit 18 are formed on a glass substrate 15 at the same time as pixel TFTs that constitute an active matrix 16. The polysilicon TFTs are formed either by a high-temperature polysilicon process in which elements are formed on a quartz substrate by a process of higher than 1,000xc2x0 C., or by a low-temperature process in which elements are formed on a glass substrate by a process of lower than 600xc2x0 C.
The polysilicon TFT can attain a mobility of larger than 30 cm2/V.s and can operate with a signal of about several megahertz in contrast to the fact that the mobility of the amorphous silicon TFT is about 0.5 cm2/V.s.
Driver circuits for driving an active matrix liquid crystal display device are classified into a digital type and an analog type. Since the number of elements needed in a digital driver circuit is much larger than in an analog driver circuit, driver circuits using polysilicon TFTs generally employ an analog scheme. Further, each of the scanning line driver circuit and the signal line driver circuit may be configured in two different ways, that is, by using a shift register or a decoder.
A driver circuit using a shift register will be described first.
FIG. 23 is a block diagram of a shift register. In a commonly used configuration of a shift register 20, a D-type flip-flop (hereinafter abbreviated as xe2x80x9cDFFxe2x80x9d) 21 is formed by combining clocked inverters and inverters. FIGS. 24A-24E show an example of a DFF. Specifically, FIG. 24A shows a circuit configuration of a DFF, FIGS. 24B and 24D show a circuit configuration of a clocked inverter 25 that is a component of the DFF, and FIGS. 24C and 24E show a circuit configuration of an inverter 26 that is another component. There is another type of DFF which uses transmission gates.
Referring to FIGS. 25A and 25B, a description will be made of a signal line driver circuit that is formed by combining a shift register, inverter-type buffers, and transmission gates (hereinafter referred to as xe2x80x9cTM gatesxe2x80x9d).
A start pulse (SP) and clocks (CL and /CL) are input to the first stage of a shift register. FIGS. 25A and 25B are a block diagram and a timing chart of the signal line driver circuit. In FIG. 25B, waveforms at points A-F in FIG. 25A are shown and t1-t8 denote time periods.
Each of periods t1-t8 is a half of the clock pulse cycle. The start pulse changes from High to Low in period t1. Since a clocked inverter 31 performs an inverter operation, a waveform at point A has a phase opposite to the phase of the start pulse. The phase of a waveform at point B is further reversed.
During period t2, the clock inverter 31 is rendered non-operating and a clocked inverter 32 operates as an inverter. As a result, at point A, the final state of period t1, i.e., Low, is maintained. At point B, where the phase is opposite to the phase at point A, the final state of period t1, i.e., High, is maintained. A clocked inverter 33 operates during period t2. As a result, Low, i.e., an opposite phase to the phase at point B, appears at point C, and High, i.e., the same phase as at point B, appears at point D.
Next, during period t3, clocked inverters 31, 34 and 35 operate and clocked inverters 32, 33 and 36 are rendered non-operating. As a result, Low, which is the same as the sate of the input start pulse, appears at point B, and the final state of period t2, i.e., High, is maintained at point D. At point F, where the phase is the same as at point D, High is maintained.
Next, during period t4, the clocked inverters 31, 34 and 35 are rendered non-operating and the clocked inverters 32, 33 and 36 operate. As a result, Low appears at points B and D, and High appears at point F. The shift register using the DFFs operates in the above manner (see FIG. 25B) to transfer signals sequentially. In FIG. 25A, reference numerals 37-39 denote clocked inverters, 52 denotes a video signal line, and 53-55 denote signal lines.
Outputs of the respective stages at points B, D and F are transferred to TM gates 49-51 via inverter-type buffers 40-48. Inverter-type buffers are used to drive large-sized transistors of a TM gate, and have a size ratio of about 1:3 in each buffer stage.
When one of the TM gates 49-51 is turned on, the video signal line 52 is short-circuited with one of the signal lines 53-55 in the matrix and a video signal is written to the signal line. The written signal is held by the signal line until the next writing, because each signal line, the opposed substrate, and the liquid crystal in between constitute a capacitor in the matrix. Where the capacitance is insufficient, a thin-film capacitor is connected to each signal line to hold a signal.
As described above, the maximum operating frequency of a shift register is about several megahertz in the case of a polysilicon TFT driver circuit. However, a signal cannot be used as it is in the case of VGA in which the reference clock frequency is 25 MHz. Even higher frequencies of 50 MHz and 100 MHz are used in XGA and EWS, which are higher level standards than VGA. Naturally the polysilicon TFT driver circuits cannot deal with a signal according to such standards. One of the following measures is usually taken to obviate this problem.
A first measure is to externally provide a sampling circuit which consists of sampling switches 61-1 to 61-8, sampling capacitors 62-1 to 62-8, and buffer amplifiers 63-1 to 63-8 as shown in FIG. 26. An input video signal is converted into parallel signals by high-speed sample-and-holding and time-division. FIG. 27 is a timing chart showing how this measure is effected for a VGA signal. In the case of VGA, a video signal varies every 40 ns as shown in part (a) of FIG. 27. This signal is sampled by sampling signals shown in parts (b)-(d) of FIG. 27, to produce signals shown in parts (e)-(g) of FIG. 27. With the above operation, the frequency can be reduced by a factor of xe2x85x9. Although this method has an advantage that the number of stages of the shift register in the signal line driver circuit can also be reduced by a factor of xe2x85x9, the necessity of an external sample-and-hold circuit imposes an additional load on the external circuitry.
A second measure is a sampling method in which a video signal is not altered, and instead the internal shift register is divided into four sections and the phases of clocks supplied to the respective shift register sections are deviated by a quarter of the cycle. Although this measure is advantageous in that no external sample-and-hold circuit is needed, it has a disadvantage that the internal driver circuit is complex. FIG. 28 shows this method, in which respective sampling periods are 320 ns.
Next, a description will be made of the scanning line driver circuit. The scanning line circuit is different from the signal line driver circuit in that the drive frequency of the former is {fraction (1/500)} to {fraction (1/1000)} of the latter, and that outputs of the scanning line driver circuit is supplied to the scanning lines via an inverter-type buffer circuit. To drive the scanning lines, no TM gates are used unlike the case of the signal line driver circuit and binary outputs of High and Low are used. FIGS. 29A and 29B are a block diagram and a timing chart of a scanning line driver circuit. In FIG. 29A, reference numerals 81-86 denote clocked inverters; 87-89, inverters; 90-92, NAND circuits; and 93-101 inverter-type buffers.
The clock frequency is about 16 kHz in the case of VGA. The shift register operates in the same manner as that of the signal line driver circuit.
Next, driver circuits using a decoder will be described.
A decoder circuit is formed by AND circuits in a logic design, but it is usually produced by combining NAND circuits and inverters or NAND circuits and NOR circuits because semiconductor devices as an implementation of NAND circuits can be produced more easily than those as an implementation of AND circuits. FIG. 30 shows a signal line driver circuit using a decoder. In FIG. 30, reference numerals 111-113 denote NAND circuits; 114-122, inverter-type buffers; 123-125, sampling analog switches. Further, reference numeral 126 denotes a video signal line, and 127-129 denote signal lines.
The decoder circuit operates in response to an input address signal, to drive a necessary TM gate. A scanning line driver circuit using a decoder is constructed and operates in similar manners (not described here).
FIG. 31 is a simplified diagram of a circuit configuration using a decoding circuit. This circuit consists of a scan control signal lines 131-1 to 131-4 and logic circuits 132-1 to 132-4. Each of the logic circuits 132-1 to 132-4 performs a logic operation on signals that are input from the scan control signal lines 131-1 to 131-4, and outputs a result of the operation. By constructing the logic circuits 132-1 to 132-4 so that they perform different logic operations, scanning signals are output in a deviated manner as shown in a timing chart of FIG. 32.
The above-described shift register type driver circuit and the decoder type driver circuit have the following problems.
In the shift register type driver circuit, input pulses are sequentially transferred in response to clocks. Therefore, if a device failure occurs at a certain stage of the driver circuit, operation failures are caused in all the following stages. Thus, this type of driver circuit likely causes a reduction in the yield rate of a display device. If it is intended to make the driver circuit redundant, the circuit configuration becomes complex.
Although being free of the above problems associated with the shift register type driver circuit, the decoder type driver circuit has other problems described below. As described above, a polysilicon TFT driver circuit is insufficient in frequency response, it is necessary to employ frequency division or multi-phase clock signals.
In the case of the decoder type driver circuit, it is difficult to employ multi-phase clock signals, while it is possible to employ frequency division though there arises the problem of addition of an external circuit (this problem also occurs in the shift register type driver circuit). For example, to use 640 signal lines of VGA without employing multi-phase clock signals, 10-bit address data is needed. Since two wiring lines are needed for each bit, a total of 20 wiring lines need to be provided to drive the decoder circuit. On the other hand, to perform 8-phase sampling on address data, addresses of 7 bits (for 80 signal lines) are needed for each phase. That is, addresses of 56 bits (8 times the above number) are needed for the total of 640 signal lines. This number is more than 5 times the number of the case where the 8-phase sampling is not employed. The number of wiring lines amounts to 112. Therefore, a large wiring area needs to be secured on a substrate. Further, there arise problems of crosstalk between wiring lines and wiring delay which is caused by the fact that each wiring line serves as a load capacitance of the other wiring lines.
In recent years, matrix-type display devices are required to perform display based on high-resolution, high-frequency video signals such as those of SVGA, XGA, and Hi-Vision. In this case, it is difficult to cause a scanning circuit, a sample-and-hold circuit, etc. to operate at a sufficiently high speed for a video signal of the above frequencies.
This problem can be solved by a technique in which, as shown in FIGS. 33 and 34, plural sets of logic circuits 132 and scan control signal lines 131 (see FIG. 31) are provided and signals of the respective scan control signal lines 131 are given different phases. This configuration enables display of a high-resolution, high-frequency video signal by causing adjacent logic circuits 132 to produce that are deviated in phase by a period shorter than the sampling pulse width and performing time-related processing on the video signal accordingly.
As is apparent from FIG. 33, this configuration has many wiring cross points because of the increase in the number of scan control signal lines 131. Since the parasitic capacitances of the wiring increase due to parasitic capacitances occurring at the cross points, this configuration is problematic not only in increase of the circuit scale but also in increase of the power consumption due to the parasitic capacitances.
Further, a variation in the characteristics of the circuits for driving the respective scan control signal lines 131 causes variations in delay and rising and falling times. As a result, a pulse signal may be output at unintended timing, causing adverse influences on the sample-and-hold circuit etc.
The present invention has been made to solve the above problems in the art, and has an object of providing a scanning circuit that constitutes a driver circuit which scanning circuit is small in circuit scale and low in power consumption by virtue of a decreased number of wiring lines required therein, and which can suppress the occurrence of glitches in outputs.
Another object of the invention is to provide a matrix-type image display device which can produce superior display images by suppressing the occurrence of glitches.
According to a first aspect of the invention, there is provided an active matrix display device comprising a number of pixels arranged in matrix form; signal lines for supplying display signals to the pixels; and a driver circuit for driving the signal lines, the driver circuit comprising a frequency divider circuit for frequency-dividing input multi-phase clock signals; a synchronous counter circuit for frequency-dividing part of the input multi-phase clock signals; and a decoder circuit for selecting a desired one of the signal lines based on outputs of the frequency divider circuit and the synchronous counter circuit.
The above active matrix display device may further comprise a level shift circuit provided upstream of the frequency divider circuit and the synchronous counter circuit, for converting an amplitude of the multi-phase clock signals.
In the above active matrix display device, the frequency divider circuit or the synchronous counter circuit may be constituted by using thin-film transistors.
In the above active matrix display device, the frequency divider circuit or the synchronous counter circuit may be constituted by using single crystal transistors.
According to a second aspect of the invention, there is provided an active matrix display device comprising a number of pixels arranged in matrix form; signal lines for supplying display signals to the pixels; and a driver circuit for driving the signal lines, the driver circuit comprising a frequency divider circuit for frequency-dividing input multi-phase clock signals; a synchronous counter circuit for frequency-dividing part of the input multi-phase clock signals; a decoder circuit divided into a plurality of decoder circuit sections; and a gate circuit for selectively supplying the respective decoder circuit sections with outputs of the frequency divider circuit and the synchronous counter circuit, wherein each of the decoder circuit sections selects a desired one of the signal lines based on the selectively supplied outputs of the frequency divider circuit and the synchronous counter circuit.
The above active matrix display device may further comprise a level shift circuit provided upstream of the frequency divider circuit and the synchronous counter circuit, for converting an amplitude of the multi-phase clock signals.
In the above active matrix display device, the frequency divider circuit or the synchronous counter circuit may be constituted by using thin-film transistors.
In the above active matrix display device, the frequency divider circuit or the synchronous counter circuit may be constituted by using single crystal transistors.
As an embodiment of the first and second aspects of the invention, a driver circuit for a liquid crystal display device is constituted by a frequency divider circuit for frequency-dividing input multi-phase clock signals; a synchronous counter circuit for frequency-dividing part of the input multi-phase clock signals; and a decoder circuit for selecting a desired one of signal lines based on outputs of the frequency divider circuit and the synchronous counter circuit.
By selectively driving the signal lines of a matrix based on a combination of the multi-phase clock signals and the decoder circuit in the above manner, the number of address signal lines of the decoder circuit can be reduced. This enables reduction in the area occupied by the driver circuit as well as reduction in the crosstalk between wiring lines. Thus, a higher quality display device can be realized.
To attain the above objects, according to a third aspect of the invention, there is provided a scanning circuit comprising L scan control signal lines to be used for setting a direction and an order of scanning; first logic circuits for producing pulse signals by performing a logic operation on signals on M of the L scan control signal lines; flip-flop circuits each being set by a pulse signal that is output from one of the first logic circuits, and reset by a pulse signal that is output from another of the first logic circuits which belongs to a stage after a stage of the one first logic circuit; N timing control signal lines for setting output timing of scanning signals that are output finally; and second logic circuits for producing the scanning signals by performing a logic operation on pulse signals that are output from the N timing control signal lines and pulse signals that are output from the flip-flop circuits.
According to a fourth aspect of the invention, there is provided a scanning circuit comprising L scan control signal lines to be used for setting a direction and an order of scanning; a glitch preventing pulse signal line for forwarding a glitch preventing pulse to be used for preventing generation of a glitch; first logic circuits for producing pulse signals by performing a logic operation on signals on M of the L scan control signal lines and the glitch preventing pulse; flip-flop circuits each being set by a pulse signal that is output from one of the first logic circuits, and reset by a pulse signal that is output from another of the first logic circuits which belongs to a stage after a stage of the one first logic circuit; N timing control signal lines for setting output timing of scanning signals that are output finally; and second logic circuits for producing the scanning signals by performing a logic operation on pulse signals that are output from the N timing control signal lines and pulse signals that are output from the flip-flop circuits.
According to a fifth aspect of the invention, there is provided a scanning circuit comprising L scan control signal lines to be used for setting a direction and an order of scanning; a glitch preventing pulse signal line for forwarding a glitch preventing pulse to be used for preventing generation of a glitch; first logic circuits for producing pulse signals by performing a logic operation on signals on M of the L scan control signal lines, or signals on M of the L scan control signal lines and the glitch preventing pulse; flip-flop circuits each being set by a pulse signal that is output from one of the first logic circuits, and reset by a pulse signal that is output from another of the first logic circuits which belongs to a stage after a stage of the one first logic circuit; N timing control signal lines for setting output timing of scanning signals that are output finally; and second logic circuits for producing the scanning signals by performing a logic operation on pulse signals that are output from the N timing control signal lines and pulse signals that are output from the first logic circuits or the flip-flop circuits.
In the scanning circuit according to any of the third to fifth aspects of the invention, L may be set equal to M.
The scanning circuit according to any of the third to fifth aspects of the invention may be constructed such that L is equal to 2M, that the L scan control signal lines are M sets of two scan control signal lines of opposite polarities, and that each of the first logic circuits uses one of the two scan control signal lines for each of the M sets.
The scanning circuit according to any of the third to fifth aspects of the invention may be constructed such that during operation of the scanning circuit, signals on the M scan control signal lines and signals on the other scan control signal lines have opposite polarities, and a combination of the M scan control signal lines having the same polarity is switched at a fixed cycle.
In the scanning circuit according to any of the third to fifth aspects of the invention, a signal on at least one of the scan control signal lines and the glitch preventing pulse signal line may be used as a signal on the timing control signal lines.
In the scanning circuit according to any of the third to fifth aspects of the invention, each of the first may produce a plural number of outputs which control flip flop circuits of the same number.
According to the invention, there is provided a matrix-type image display device comprising a data signal line driver circuit and a scan signal line driver circuit, at least one of the data signal line driver circuit and the scan signal line driver circuit comprising the scanning circuit according to any of the third to fifth aspects of the invention.
The operation and advantages of the third to fifth aspects of the invention will be described below.
In the invention, since scanning signals are produced by performing logic operations on outputs of the flip-flop circuits and signals on the timing control signal lines, it is not necessary to provide plural systems of scan control signal lines having different phases. This enables reduction in the number of signal lines. As a result, the number of wiring cross points is decreased and the parasitic capacitances occurring in the wiring is reduced. Thus, the power consumption can be reduced from the conventional case.
By designing the flip-flop circuits so that they are not set or reset unless they receive a pulse sufficiently wider than glitches that may be generated by the first logic circuits due to timing deviations in signals on the scan control signal lines, erroneous operation of the flip-flop circuits can be avoided, thereby allowing scanning signals to be output at the required timing.
Alternatively, by inputting a glitch preventing pulse to the first logic circuits, the glitch generation itself can be avoided. Therefore, erroneous operation of the flip-flop circuits can be avoided, thereby allowing scanning signals to be output at the required timing.
Similarly, scanning signals can be produced at the required timing without causing glitches with a relatively simple circuit configuration by inputting a glitch preventing pulse to the first logic circuits to suppress generation of glitches to thereby prevent erroneous operation of the flip-flop circuits, and by producing scanning signals by performing logic operations on outputs of the first logic circuits or the flip-flop circuits and signals on the timing control signal lines.
The number of signal lines can be minimized by a configuration which satisfies a relationship L=M where L is the total number of scan control signal lines and M is the number of scan control signal lines used by the first logic circuits.
Alternatively, there may be employed a configuration in which L is equal to 2M, the L scan control signal lines are M sets of two scan control signal lines of opposite polarities, and that each of the first logic circuits uses one of the two scan control signal lines for each of the M sets. In this case, the first logic circuits, the second logic circuits, and the flip-flop circuits of the respective stages can have the same configuration.
As a further alternative, there may be employed a configuration in which during operation of the scanning circuit, signals on the M scan control signal lines and signals on the other scan control signal lines have opposite polarities, and a combination of the M scan control signal lines having the same polarity is switched at a fixed cycle. In this case, the number of scan control signal lines can be made as small as possible, and at least the first logic circuits of the respective stages can have the same configuration.
In the scanning circuit according to any of the third to fifth aspects of the invention, a signal on at least one of the scan control signal lines and the glitch preventing pulse signal line may be used as a signal on the timing control signal lines. This enables further reduction in the number of signal lines.
In the scanning circuit according to any of the third to fifth aspects of the invention, each of the first may produce a plural number of outputs which control flip flop circuits of the same number. This reduces the total number of elements, thereby simplifying the configuration of the scanning circuit.
The scanning circuit according to any of the third to fifth aspects of the invention may be used in at least one of a data signal line driver circuit and a scan signal line driver circuit of a matrix-type image display device. This configuration can reduce the power consumption and prevent occurrence of glitches, thereby providing superior display images.